It will become the basis of Shared Bus. Though the analysis about the PowerPC Bus, there are four parts in BIU: Instruction Pretreatment Part, Address Bus Treatment Part, Data Bus Treatment Part and Data Pos-treatment Part. 通过对PowerPC结构的总线协议的分析,总线接口部分主要由指令预处理部分、地址总线处理部分、数据总线处理部分和数据后处理部分组成,完成微处理器和外部总线的数据交互。
A bus shared heterogeneous architecture consisting of one or more instruction set processor cores, one or more dedicated hardware IP cores and one or more on-chip memories usually provides a good solution. 基于总线互连的由一个或多个指令集处理器核、一个或多个专用硬件IP核、一片或多片片上存储器构成的异质体系结构成为媒体系统芯片的合理选择。
The design of shared data register file is the hardest for implementation of VLIW ( Very Long Instruction Word) DSP ( Digital Signal Processing) Processors. 共享数据寄存器堆设计是超长指令字DSP处理器实现的难点。
The experiment is composed of a whole series of shared activities on the part of both teachers and students, and some specific cases of writing classroom instruction. 整个实验过程,贯穿着一系列的师生之间和学生之间的共同活动以及具体的写作课案例。